1. Field of the Invention
The present invention generally relates to a method for forming multi-level interconnect in an integrated circuit, and more particularly to a method for forming a via-first dual damascene interconnect structure by using gap-filling materials whose thickness is controlled by a developer.
2. Description of the Prior Art
As feature sizes shrink, more devices can be built per unit substrate area. The multi-layer interconnects are employed in order to accommodate higher densities as device dimensions shrink well below one micron design rules. Through advanced semiconductor processing techniques, integrated circuit devices with sub-micron and sub-half-micron features have driven the need for multi-layer interconnects. At the same time, the size of interconnect structures will also need to shrink, in order to accommodate the smaller dimensions. Thus, as integrated circuit technology advances into the deep sub-micron range, more advanced interconnect architecture and application are required.
Damascene integration scheme is one such architecture to satisfy this need. The main advantage of the damascene process is the elimination of the need to etch the metal layer that provides the interconnections. Another advantage is that it can eliminate the need for a dielectric gap fill. A third advantage is that it avoids some of the problems associated with lithographic overlay tolerance, making it possible to achieve higher interconnect packing density. There are two major classes of damascene processes: single-damascene and dual-damascene. A single damascene process involves making contact to a lower conductive layer by patterning dielectric layer and forming a conducting plug in the dielectric layer, then patterning a second dielectric layer and forming the actual interconnect wiring metallization in the dielectric layer. The dual damascene technology is applied, as integrated circuit technology advances to 0.18 micrometer. In a dual damascene process, the interconnect wiring and plug are formed by patterning both the via and the trench patterns into dielectric layer, then filling them simultaneously with conducting material, such as metal. The dual damascene process offers an advantage in process simplification and low manufacturing cost by reducing the process steps required to form the vias and trenches for a given metallization level. The openings, for the wiring of a metallization level and the underlying via connecting the wiring to a lower conducting level, are formed at the same time.
Dual damascene integration requires challenging developments of patterning processes. Both lithography and etch become more difficult due to complex layer stack and intermediate topography. Therefore, many different dual damascene patterning strategies are possible, leading to a similar topography before the conducting material is placed. Many dual damascene process flows depend upon the sequence of basic etch steps, which defines a dual damascene process flow as self-aligned, trench-first, or via-first. Self-aligned dual damascene (SADD) needs a thick intermediate layer to serve as a photo anti-reflection layer, an etch-stop layer, and a hard mask providing CD control for underlying vias. Because self-aligned vias require almost perfect trench-to-via alignment and the challenge of maintaining a very high selectivity between the dielectric and intermediate stop layer when etching the via, its application is limited. In the approach of trench-first dual damascene (TFDD), the trench is masked and etched through the dielectric with stop at a timed depth. The via pattern is then aligned with trench and etched through the dielectric to the lower conductive layer. Achieving a very uniform trench with a smooth flat etch front and maintaining via critical dimension control are the specific etch challenges assorted with trench-first flow. In the via-first dual damascene (VFDD), the via lithography is done first on top of the full stack. After via-etch and strip, the trench photo step is done. In some cases, the bottom of via is covered by a gap-filling material, such as an organic anti-reflective coating, to protect via during the trench etch.
It is well known that reflection control is essential in lithography processing. Unwanted reflections from these underlying materials during the photoresist patterning process cause the resulting photoresist pattern to be distorted. The use of a bottom-anti-reflective coating (BARC) is pursued in the integration of dual damascene not only to prevent distortion of photoresist pattern but also to act as the gap-filling material. However, by use of BARC as the gap-filling material in the VFDD process, several concerned problems are occurred. While a BARC is in contact with low k dielectric layer in via, a chemical interaction takes place within the via forming a thin residue which induces an incomplete trench etch with the fence problem. As shown in FIG. 1, a low k dielectric layer 120 is formed on a substrate 100 having a conductive structure 110, and the fence problem 130 is appeared when using BARC as the gap-filling material. Moreover, when a gap-filling material containing nitrogen atom is in contact with a low k dielectric layer, the value of k will increase due to the diffusion of nitrogen atom. After creating via openings, local reflectivity changes occur over the substrate. This is not only the result of local reflectivity variations, but also of the severe resist thickness variations, due to changes in feature topography density. A possible solution is the use of an organic BARC, which helps on one hand to make the reflectivity again more uniform, but on the other hand to decrease the step height on the surface.
However, in the VFDD process, using BARC as the gap-filling material results in trench profile distortion due to the rough topography, which suffers lithography process window. In conventional techniques using BARC filling vias, it is difficult to fill both isolated and dense vias in a similar way. The BARC coating level is very different depending very much on the feature density and size. Referring to FIG. 2, which shows a dielectric layer 220 is formed on a substrate 200 having conductive structures 210 by using BARC 230 as the gap-filling material. For some cases, the via 232 is not fully filled, void occurs inside the covered via 234, or a rough topography is presented. In order to avoid the formation of fences during the trench etching, controlling the gap-filling material thickness is very important. Special care for controlling the BARC thickness to prevent the fence problem is developed by complex etching process in the prior art. However, it is highly desirable to use a gap-filling material which easily fills gaps, is free of nitrogen atom and easy for its thickness control, in that it exhibits excellent planarity, gap-filling capacity, and fence-free structure in the dual damascene process.
The present invention is directed to a method for forming via-first dual damascene interconnect structure by using gap-filling materials whose thickness is easily controlled by a developer to prevent fence problem. The gap-filling materials include novolak, PHS (poly hydroxy styrene), acrylate, methacrylate, and COMA (cyclo alicylic co-polymer with maleic anhydride). The advantage of using novolak as the gap-filling material is to get a fine planar topography for larger process window due to its excellent gap-filling capacity. Another advantage is that novolak free of nitrogen atom is good for low k material application in the dual damascene process. A third advantage is that novolak is easily dissolved in a developer, such as 2.38% TMAH (tetramethylammonium hydroxide) solution, and the thickness of novolak in via can be easily controlled by fine-tuning the removal time to prevent the fence problem from forming.
It is another object of this invention that a method for protecting the bottom of via by using gap-filling material is provided.
It is a further object of the present invention that a method for eliminating the need to etch gap-filling material thickness in via is provided.
In accordance with the present invention, in one embodiment, a method for forming a via-first dual damascene interconnect structure is disclosed by using novolak as the gap-filling material is disclosed. The method comprises the step of providing a substrate having a conductive structure. Then, a dielectric layer is formed on the substrate. A first patterned photoresist is then formed on the dielectric layer, wherein the first patterned photoresist defines a via opening. Next, the dielectric layer is etched to expose the conductive structure of the substrate by using the first patterned photoresist as a mask. Then, the first patterned photoresist is removed. The key aspect of the present invention is that a novolak layer is formed on the dielectric layer and fills the via. Then, the novolak layer is chemical mechanical polished to expose the dielectric layer. A BARC layer is formed on the dielectric layer. Then, a second patterned photoresist is formed on the BARC layer, wherein the second patterned photoresist defines a trench opening, and the BARC layer is etched to form the trench pattern. Then, a portion of the novolak layer is time-removed by a developer to a depth about the desired trench opening level, which is about half thickness of the dielectric layer. Then, an upper portion of the dielectric layer is etched to form the trench opening in the dielectric layer. The second patterned photoresist, the BARC layer, and the novolak layer are removed. Then, the first opening and the second opening are filled with a conductive material to form a conductive layer.